The present invention relates to an interface between unsynchronised devices.
The invention is particularly relevant to the interface between Application Specific Integrated Circuits (ASICs) and/or processors, which operate on unsynchronised system Clocks.
In order for a device such as a processor or second ASIC to change the register contents of a sending device such an ASIC comprising, for example a plurality of flip-flops, requires data to be presented to the second ASIC along with an address and a write strobe (WS). The second ASIC is, for the context of this document, considered to be clocked by a signal referred to as the ASICClock signal, to which the transferred data must ultimately become synchronised.
The address, write strobe (WS) and data signals are all synchronous to the sending device.
An address decode circuit on the ASIC will decode the incoming address, to generate register selects for every register.
The write strobe (WS) is used to latch the incoming data into a preliminary register, synchronous to the sending device, but physically existing on the ASIC (receiving device). The data in this register must then be transferred to a secondary register, clocked by the ASICClock signal.
A common problem with unsynchronised transfers is that when the data input to a flip-flop or latch changes at the same time as the clock or enable, the output can attain a condition referred to as metestability, which is an unpredictable, unstable state.
Therefore, when data is written into a register care must be taken to write the data when the ASICClock signal of the register is in an active state when data can be accurately and unambiguously written into the register. That is data should not be written into the register when the clock pulse is on its active transaction, i.e. either rising or falling depending on the device as this will lead to uncertainty as to whether or not the information will be stored correctly in the register. This is a problem particularly when data is being transferred between a first ASIC device and a second ASIC device which operate on different clocks.
According to the prior art, as illustrated in FIG. 1, the solution to the problem of metastability is to use three banks of flips flops 1,2,3, the first bank 1 being clocked by the sending device clock (the write strobe 4 in this instance), and the second and third banks 2 and 3 being clocked by the receiving clock (ASICClock). In this fashion although the data from the second bank 2 may be metestable, it will almost certainly be stable by the time the third bank 3 latches or clocks it in.
Regarding FIG. 1, data 16 from, and synchronous with the system clock of, the first ASIC 9 is supplied to the interface along with an address signal, and a write strobe (WS) signal. Data is presented to whichever register is selected by the address signal, after the address signal is decoded in the address decode logic 5.
A problem with this solution is the overhead in substrate real-estate (i.e., the excessive use of substrate surface area), because for every register in the ASIC there must be two extra registers of the same data width for the resynchronisation process. As well as the real-estate overhead, a significant power consumption overhead is incurred, due to the increased number of registers being clocked continually. This is a particular problem with devices in battery operated apparatus wherein the operating time of the apparatus before the battery is depleted is reduced by the excessive power drain.